Application Layer: Principles of Network Applications, The Web and HTTP, File Transfer: FTP, Electronic Mail in the Internet, DNS—The Internet's Directory Service, Peer-to-Peer Applications.
Transport Layer: Connectionless Transport: UDP, Principles of Reliable Data Transfer, Connection-Oriented Transport: TCP, Principles of Congestion Control, TCP Congestion Control.
Network Layer: Virtual Circuit and Datagram Networks, The Internet Protocol (IP), Addressing and Subnetting, Routing Algorithms, Internet Routing Protocols, Spanning Tree Algorithms, Principles of Mobility Management and Mobile IP.
Link Layer and Local Area Networks: Services and Multiple Access Protocols, ARQ strategies, analysis of ARQ strategies, Ethernet: 802.3, Wi-Fi: 802.11 Wireless LANs.
Delay Models in Data Networks (Ref: 2, Chapter 12):
Little's theorem, Single and multiple servers queuing models, Network of queues (Jackson's theorem).
References:
Computer Networks by Andrew Tanenbaum, Prentice Hall; 5 edition, 2010.
Probability, Statistics, and Random Processes for Electrical Engineering by L. Garcia, Prentice Hall; 3rd edition, 2008.
Public Key Infrastructure (PKI) and Digital Signatures: RSA algorithm, Public key certificates and the X.509 standard, Message digests, Symmetric and asymmetric (public key) digital signatures, Certificate authorities and trust models, Attacks on digital signature schemes.
Security Protocols: Simple authentication mechanisms, Real-world security protocols (Kerberos, SSL/TLS, IPsec, SSH), Protocol vulnerabilities and known attacks.
Principles of access control, user authentication, and authorization
References:
Information Security: Principles and Practice by Mark Stamp, Wiley, 2nd Edition, 2011.
Understanding Cryptography: A Textbook for Students and Practitioners by Christof Paar and Jan Pelzl, Springer, 1st Edition, 2010.
Area 3: Digital Systems Design
Fundamentals of Digital System Design: Combinational and sequential logic, Moore and Mealy machines, Datapath and control unit design.
Hardware Modeling and Hardware Description Language: Design hierarchy, partitioning, and top-down design. Modeling constructs—structural, behavioral, and RTL models. Modeling iterative/regular structures and test benches. Design organization and parameterization. HDL coding for synthesis.
High-Level Synthesis: Data flow and control sequencing graphs, data-flow-based transformations (optimizations), architectural synthesis, resources and constraints, scheduling, time-constrained scheduling, resource-constrained scheduling. Heuristic scheduling algorithms such as list scheduling. Allocation and binding, resource sharing, register sharing. Datapath and control unit synthesis. Pipelining.
References:
M. D. Ciletti, "Advanced Digital Design with the Veilog HDL," (Prntic Hall), 2/e 2010.
Synthesis and Optimization of Digital Ciruits – Giovanni De Micheli, MGrw Hill Intenational Edition, ISBN –0-07-113271-6, 1994. (Chaptes 4-6).
Area 4: Computer Architecture
Fundamentals of Quantitative Design and Analysis
Evaluation Metrics: Performance, Power & Energy, and Area & Cost.
Summarizing Performance and Benchmarking; geometric/harmonic means, calculating speedups, normalizing performance.
Computer Architecture Trends:
Yield, Moore’s Law, Dennard Scaling, and Memory Wall.’ISA (MIPS Architecture)
ISA classifications
ISA design: encoding, decoding, formats, and addressing modes.
Functions and Function Calling Convention (Supporting Nested-Function Call)
Program IO (System Calls)
Pointers and Multi-Dimensional Arrays.
Programming Algorithms in Assembly Language: From Pseudo-Code to Assembly.
Computer Organization and Architecture
CPU Performance Analysis (Iron Law of Processor Performance)